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r07ds0892ej0001 rev.0.01 page 1 of 17 nov 29, 2012 preliminary datasheet raa207703gbm/7704gbm/7705gbm synchronous buck regulator with internal power mosfets description the raa207703gbm is monolithic synchronous buck regulator with power mosfets in extremely small package. the raa207703gbm delivers high output current by small rds(on) power mosfets. constant on time control architecture provides fast transient response, and minimize external components. the raa207703gbm operates skip mode at light load, it provides high efficiency in all lo ad condition. the raa207703gbm incorporates internal 5v ldo, so the regulator can operates single power supply. three current ability products can be selected. features ? input voltage range: 5.5 v to 16 v ? constant-on-time control ? built-in power mosfets suitable for pc, server application ? internal 5 v ldo for single power supply operation ? 5 v ldo / external 5 v input selectable (ldo remote on/off) ? switching frequency: adjustable up to 2 mhz ? high average output current, up to 15 a (7703gbm), 10 a (7704gbm), 5 a (7705gbm) ? controllable driver: remote on/off ? power good function ? over current protection/over voltage protection/thermal shutdown function ? built-in bootstrapping diode ? soft start period adjustable ? enhanced light load mode function for higher efficiency ? extremely small chip size package with solder bump ? pb-free/halogen-free application circuit vcc on/off pgood v5_in sgnd vin sw pgnd boot vin raa207703gbm raa207704gbm RAA207705GBM ss ldo_en# vout set fb r07ds0892ej0001 rev.0.01 nov 29, 2012 www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 2 of 17 nov 29, 2012 pin arrangement top view vcc sw sw sw sw sw boot vin vin vin sgnd vcc vcc vcc set sw pgo od sw sw sw sw ss on/ off fb vin vin ldo_ en# ldo_ en# ldo_ en# ldo_ en# v5_ in v5_ in v5_ in v5_ in vcc ldo_ en# v5_ in vcc ldo_ en# v5_ in boot sgnd set pgo od ss on/ off fb boot sgnd set pgo od ss on/ off fb a a a 12345 12345 12345 g f e d c b f e d c b d c b pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw sw vin vin vin sw sw sw sw sw sw sw sw sw vin vin vin vin vin pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd <RAA207705GBM> bottom view sw sw sw sw sw boot vin sgnd pgo od sw sw sw ss fb vin a a a 54321 54321 54321 g f e d c b f e d c b d c b pgnd pgnd pgnd pgnd pgnd set sw sw vin pgnd pgnd vin vin on/ off boot sgnd pgo od ss fb set on/ off boot sgnd pgo od ss fb set on/ off pgnd pgnd pgnd sw sw sw sw vin sw sw sw vin pgnd pgnd pgnd sw sw vin pgnd vin vin pgnd pgnd sw sw sw sw vin vin vin pgnd pgnd pgnd <RAA207705GBM> csp 35-pin package 2.7 mm 3.9 mm csp 30-pin package 2.7 mm 3.4 mm csp 20-pin package 2.7 mm 2.4 mm www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 3 of 17 nov 29, 2012 pin description pin name pin no. description remarks vcc 1a controller voltage controller supply input (5 v regulator output) sgnd 2a controller analog gnd should be connected to pgnd on pcb pattern fb 3a feedback voltage input pin v5_in 4a 5 v external input ldo_en# 5a internal 5 v ldo enable pin boot 1b bootstrap voltage pin to be supplied +5 v through integrated sbd set 2b constant on time program pin tie resistor between sw and set pgood 3b power good indicator pin pull low when no good (open drai n output) ss 4b soft start period program pin tie capacitor between ss and sgnd on/off 5b operation enable pin oper ation stop when l signal asserted vin ? input voltage sw ? switching node pgnd ? power ground should be connected to sgnd on pcb pattern note: pin assign of 1a-5a & 1b-5b is common thro ugh raa207703gbm, raa207704gbm and RAA207705GBM. www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 4 of 17 nov 29, 2012 block diagram control logic enable tsd uvlo boot on/off 1m enable 1m tsd tsd uvlo uvlo 4.3 v ovp 0.8 v 1.0 v 2.5 a fault fault enable uvlo ripple comparator + ? + ? + 0.72 v ? + 1 shot timer delay ovp ocp tsd fault protection function sw pgnd vcin zcd comparator zcd ovp ? + ocp vcc vin v5_in set sgnd fb pgood ss ldo_en# 5v ldo 1. truth table for the on/off pin 2. truth table for ldo_en# pin on/off input driver chip status ldo_en# input 5 v regulator status "l" shutdown (operation stop) "l" ldo enable "open" shutdown (operation stop) "open" ldo enable "h" enable (normal operation) "h" ldo disable www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 5 of 17 nov 29, 2012 absolute maximum ratings (ta = 25c) item symbol ratings unit notes input voltage vin ?0.3 to +20 v 1 switch node voltage sw 20(dc), 23(<10 ns) v 1 boot voltage vboot 25(dc), 28(<10 ns) v 1, 2 controller voltage vcc ?0.3 to +6 v 1 vcc current icc ?20 to +0.1 ma 3 v5_in voltage v5_in ?0.3 to +6 v 1 fb pin voltage v fb ?0.3 to vcc +0.3 v 1, 4 on/off voltage v on/off ?0.3 to vin v 1 ldo_en# voltage v ldo_en# ?0.3 to vin v 1 set voltage v set ?0.3 to vin v 1 pgood voltage v pgood ?0.3 to vin v 1 pgood sink current i pgood +2 ma 3 operating junction temperatur e tj-opr ?40 to +125 c storage temperature tstg ?55 to +150 c notes: 1. rated voltages are relative to voltages on the sgnd and pgnd pins. 2. boot ? vcin < 20 v 3. for rated current, (+) i ndicates inflow to the chip and (?) indicates outflow. 4. vcc + 0.3 v < 6 v recommended operating condition item symbol ratings unit remarks input voltage vin 5.5 to 16 v when 5 v ldo use controller voltage vcc 4.5 to 5.5 v cont roller voltage is supplied externally continuous output current iout 0 to 15 0 to 10 0 to 5 a 15 a: raa207703gbm 10 a: raa207704gbm 5 a: RAA207705GBM www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 6 of 17 nov 29, 2012 electrical characteristics (ta = 25c, vin = 12 v, unless otherwise specified) item symbol min typ max unit test conditions vin start threshold vh ? 4.3 4.6 v vin shutdown threshold in ccm vl 3.6 3.8 ? v vin shutdown threshold in ell mode v lccm ? 3.0 3.6 v in ell mode (dcm, f sw < 100 khz) vin quiescent current iq ? 400 500 ? a output = no load, ell mode vin disable current (ldo_en# = 12 v) i in-disbl1 ? 70 150 ? a on/off = 0 v, ldo_en# = 12 v supply vin disable current (ldo_en# = 0 v) i in-disbl2 ? 130 200 ? a on/off = 0 v, ldo_en# = 0 v disable level v disbl ? ? 0.6 v 3.3 / 5.0 v interface enable level v enbl 2.0 ? ? v remote on/off pull-down resistance r disbl 0.7 1 1.3 m ? on/off = 1 v 5 v ldo on level v ldo_on ? ? 0.6 v 5 v ldo off level v ldo_off 2.0 ? ? v 5 v ldo enable pull-down resistance r ls_in 0.7 1 1.3 m ? ldo_en# = 1 v 5 v ldo output 5 v ldo output voltage v ldo 4.5 5.0 5.5 v vin = 12 v comparator threshold voltage v fb_comp 792 800 808 mv fb fb input current i fb_in ?0.1 0 +0.1 ? a fb = 1 v rising threshold on fb v pg_rise 0.67 0.72 0.77 v power good hysteresis dv pg ? 50 ? mv power good indicator power good resistance r pg 0.25 0.5 1 k ? fb = 0 v soft start soft start bias current i ss 1.8 2.5 3.2 ? a over voltage protection ovp trip voltage on fb v ovp 0.95 1.00 1.05 v ocp trip current (raa207703gbm) i ocp 16.0 20.0 24.0 a fixed internally * 1 ocp trip current (raa207704gbm) i ocp 12.0 15.0 18.0 a fixed internally * 1 over current protection ocp trip current (RAA207705GBM) i ocp 6.4 8.0 9.6 a fixed internally * 1 tsd trip temperature t tsd 130 150 ? c * 1 over temperature protection temperature hysteresis t hys ? 30 ? c * 1 note: * 1 not directly tested. assured by related characteristics test. www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 7 of 17 nov 29, 2012 description of operation the raa207703gbm operates as voltage-ripple based constant on time control architecture. converter output is controlled by output voltage ripple which is determined by inductor ripple current and es r & esl of output capacitor. each switching cycle starts high-side mosfet turn on which time is decided by 1 shot timer. after high-side mosfet turns off, low side turns on, and it keeps until fb voltage becomes lower than reference voltage. in light load condition, low-side mosfet on time is decided by inductor zero current. switching frequency, constant on time setting sw set rset switching frequency in ccm mode is determined by following equation. switching frequency: (vo/vin) ? (1/ton) [hz] here, ton is high-side mos on time, and it is determined by following equation. on time pulse: (5 pf / vin ? 2.0 v) ? rset + 50 ns [s] from above equation, constant on time is change depend on vin, so switching frequency is almost constant when vin change. this architecture is suitable for battery application. from the above equation, rset is calculated by rset: (vout / (vin ? fsw) ? 50 ns) ? (vin ? 2.0 v) / (50 pf ? 1 v) [ ? ] 100 300 500 700 900 1100 1300 1500 1700 0 50 100 150 200 250 rset [k] on time [ns] vin = 12 v vin = 5 v on time [ns] 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 4 6 8 10121416 vin [v] rset = 30 k www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 8 of 17 nov 29, 2012 maximum duty cycle operation maximum duty cycle is restricted by following equation. max. duty: 1 ? (50 ns ? fsw) here, fsw is switc hing frequency. if fb voltage does not reach reference voltage after th e high-side mosfet turn on time is expired, low-side mosfet turns on 50 ns, and next switching cycle starts. esp ecially, this condition occurs when output load transient state. sw il (inductor current) 50 ns soft start ss sgnd css soft start ramp period is adjustable by external capac itor (css) selection. when converter start operating, 2 ? a current from ss pin charges capacitor between ss and gnd. soft start period is determined by following equation. soft start period: css ? 0.8 v / 2.5 ? a [s] here, 0.8 v is internal reference voltage vref. ic operates diode emulation mode at soft start period, so it can prevent from reverse current when pre-bias condition. soft start rest arts when enable signal re-e ntered, and after ocp, ovp, tsd, uvl release condition. power good indicator power good indicator is useful for controlling multi-converter systems for sequential start up and shut down. fb voltage ismonitored continuously by power good comparator. the power good comparator compares fb pin and 90% internal referencevoltage (0.72 v). when fb reaches reference voltage, pgood pin be comes high impedance after internal delay (30% of soft start period). under the fault cond ition (uvlo, ovp, ocp, tsd) , pgood pin is pulled low. 0.72 v 0.80 v soft start period power good delay (30% soft start period) ss fb vout pgood www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 9 of 17 nov 29, 2012 over voltage protection (ovp) when fb voltage exceeds 125% of reference voltage (1.0 0 v), switching stops immedi ately and latched low-side mosfet on state in order to pull the output voltage. to leave the ovp condition, vcin needs to be pulled under the uvlo level, and re-enter the signal. fb 125% vref high mosfet signal low mosfet signal on/off (uvl) pgood 90% vref delay over current protection (ocp) ocp detection circuit monitors high-side mosfet drain-source current. when the current exceeds fixed level eight time, ic starts hiccup operation. in the hiccup operation, switching stops and operate 1 ms timer. after 1 ms timer is expired, ic operates again from soft start state. if ic dete ct ocp in the soft start circuit, hiccup operation start again. sw il 0 a ocp level 1 ms wait 1 ms wait ss pgood ocp detect note: pgood pin is connected vcc through resistor. www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 10 of 17 nov 29, 2012 thermal shutdown (tsd) thermal sensor monitors junction temperature of ic. when junction temperature exceeds 150c, switching stops. after junction temperature become 125c, ic restart switching from soft start (non-latched function). enhanced light load function (ell) ic operates diode emulation mode in light load condition. to enhance light load efficiency, ic detects light load condition automatically, and operate as enhanced light load mode (ell). in ell mode, bi as current of ic becomes small, so this function can improve the efficiency. controller power supply the raa207703gbm incorporat es internal 5 v ldo, so it can operat e with single power supply. ldo_en# can control ldo operation, and select the controller power supply from ldo or v5_in pin. when ldo_en# = h state, external 5 v should be applied to v5_in pin. typical pin connection of each operation are below. operation with single power supply operation with multi power supply ldo_en# vcc v5_in (open) vin vin ldo_en# vcc v5_in vin 5 v vin ldo loss reduce circuit (only for vout = 5 v) when regulator output is 5 v, ic can operate with their output voltage in order to reduce ldo loss. in this time, pgood signal can be used for ldo or 5v_i n select signal. pin connection is below. operation with 5 v output voltage pgood sw on/off vout = 5 v ldo_en# vcc v5_in vin vin initially, controller voltage is supplied from vin through intern al ldo. switching regulator starts from soft-start and power good output becomes hi-impedance when output 5 v becomes stable. after ldo_en# detects hi level, ldo stops and controller operates their own 5 v output voltage. www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 11 of 17 nov 29, 2012 stability criteria, output voltage se tting for high esr output capacitor small output ripple voltage makes control loop unstable in constant on time architecture. ripple voltage needs to be larger than 15 mv on fb pin. when using high esr (>50 m ? ) capacitor such as electro lytic capacitor, polymer aluminum capacitor for output capacitor, ripple voltage on fb pin will be more than 15 mv. sw fb vout r1 r2 cout lout vin esr stability criteria from loop stability analysis, constant on time control system must satisfy below equation. stability criteria: esr ? cout > ton / 2 here, ton is constant on time. if the system cannot satisfy above equation, subharmonic oscillation will occur. vout setting fb comparator compares fb voltage and internal accurate reference voltage (0.8 v). feedback loop controls fb voltage to match the reference voltage. therefore, out put voltage is set by following equation. vout: 0.8 v ? (r1+r2) / r2 here, r1 and r2 is output voltage divider resister (refer to above figure). however, ripple voltage on fb pin affects fb voltage, so vout slightly shifts from setting value. if the system needs high accuracy, adjust vout by changing r1, r2 value. www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 12 of 17 nov 29, 2012 operating with small esr output capacitor when using low-esr output capacitor like mlcc, voltage ripple on output voltage node is very small. so voltage ripple needs to be enhanced by additional components. recommended ripple enhance method is like below figure. vout rf cf cr sw fb vin lout r1 r2 cout ripple injection on fb pin rf and cf make ripple voltage using inductor dcr ripple. cr is used for ac ripple injection to fb pin. ripple voltage between rf and cf is described by following equation. vripple: (vin ? vout) ? ton / (rf ? cf) make sure above ripple voltage is larger than 15 mv. stability criteria from loop stability analysis of abov e circuit configuration, the syst em must satisfy below equation. stability criteria: lout ? cout / (rf ? cf ) > ton / 2 if the system cannot satisfy above equation, subharmonic oscillation will occur. vout setting output voltage setting is basically same concept as high esr capacitor use case. ripple voltage from injection circuit affects fb voltage, so it need to be ad just r1, r2 for high accuracy system. www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 13 of 17 nov 29, 2012 board layout example (raa207703gbm) top layer (top view) inductor input cap. output cap. raa207703gbm vin plane gnd plane vout plane sw plane www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 14 of 17 nov 29, 2012 representative inductors maker inductance [ ? h] ? l/l0 = 20% change [a] dimensions [mm] 0.42 20.0 6.7 ? 8.0 ? 4.0 0.60 19.0 6.7 ? 8.0 ? 5.0 0.88 24.0 10.0 ? 11.5 ? 4.0 nec tokin mpc series 1.0 25.0 10.0 ? 11.7 ? 5.5 0.47 13.9 * 1 6.5 ? 7.4 ? 3.0 1.0 10 * 1 6.5 ? 7.4 ? 3.0 alps green device glmc series 1.5 8.8 * 1 6.5 ? 7.4 ? 3.0 0.33 15.9 6.7 ? 7.4 ? 3.0 0.47 15.6 6.7 ? 7.4 ? 3.0 0.75 10.9 6.7 ? 7.4 ? 3.0 toko fdve0630 series 1.0 9.5 6.7 ? 7.4 ? 3.0 0.35 14.9 5.0 ? 5.2 ? 3.0 0.47 11.0 5.0 ? 5.2 ? 3.0 tdk spm5030 series 0.75 9.7 5.0 ? 5.2 ? 3.0 note: * 1 30% change ? small size inductor for raa207702gbm maker inductance [ ? h] ? l/l0 = 30% change [a] dimensions [mm] 0.68 8.3 4.2 ? 4.2 ? 2.0 1.0 6.8 4.2 ? 4.2 ? 2.0 toko fdsd0420 series 1.5 5.7 4.2 ? 4.2 ? 2.0 0.47 8.3 4.4 ? 4.1 ? 1.2 tdk spm4012 series 1.0 4.8 4.4 ? 4.1 ? 1.2 representative output capacitors maker maximum voltage [v] capacitance [ ? f] sanyo poscap series 2.0 to 10 47 to 330 sanyo os-con series 2.0 to 10 47 to 330 murata mlcc series 6.3 to 10 22 to 47 tdk mlcc series 6.3 to 10 22 to 47 taiyo yuden mlcc series 6.3 to 10 22 to 47 www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 15 of 17 nov 29, 2012 package dimensions ? raa207703gbm 4 0.05 b b a c d e f 2 43 1 5 g a seating plane c area 0.08 s c area s 0.05 m s ab 35-0.320.05 2.67 0.05 0.335 0.05 2.0 0.5 0.5 0.33 3.34 0.67 0.67 0.5 0.5 0.5 0.335 0.05 3.87 0.05 0.265 0.05 0.235 0.04 0.4 0.04 0.265 0.05 www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 16 of 17 nov 29, 2012 ? raa207704gbm 4 0.05 b a c d e f a c area c area s 30-0.320.05 b 2 43 1 5 0.08 s 0.05 m s ab 2.67 0.05 0.335 0.05 0.335 0.05 2.0 0.5 0.5 0.08 0.5 0.5 3.37 0.05 0.265 0.05 0.235 0.04 0.4 0.04 2.84 0.67 0.67 0.265 0.05 seating plane www.datasheet.net/ datasheet pdf - http://www..co.kr/
raa207703gbm/7704gbm/7705gbm preliminary r07ds0892ej0001 rev.0.01 page 17 of 17 nov 29, 2012 ? RAA207705GBM c area 4 0.05 c area s a b 20-0.320.05 a b c d 2 43 1 5 0.08 s 0.05 m s ab 2.67 0.05 0.335 0.05 0.335 0.05 2.0 0.5 0.25 2.37 0.05 0.5 0.265 0.05 0.235 0.04 0.4 0.04 1.84 0.67 0.67 0.265 0.05 seating plane www.datasheet.net/ datasheet pdf - http://www..co.kr/
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